| 1 | fn test_inline_array_index_assign_uses_full_expression() { |
| 2 | mut ram := []u8{len: 0x10000} |
| 3 | rom := [u8(0x00), 0x12, 0x00, 0x00] |
| 4 | pc := 0 |
| 5 | value := u8(0x0f) |
| 6 | |
| 7 | address := u16(rom[pc + 2]) << 8 | u16(rom[pc + 1]) |
| 8 | ram[address] = value |
| 9 | assert ram[0x0012] == value |
| 10 | assert ram[0] == 0 |
| 11 | |
| 12 | mut ram2 := []u8{len: 0x10000} |
| 13 | ram2[u16(rom[pc + 2]) << 8 | u16(rom[pc + 1])] = value |
| 14 | assert ram2[0x0012] == value |
| 15 | assert ram2[0] == 0 |
| 16 | } |
| 17 | |
| 18 | fn test_inline_fixed_array_index_assign_uses_full_expression() { |
| 19 | mut ram := [0x10000]u8{} |
| 20 | rom := [u8(0x00), 0x12, 0x00, 0x00]! |
| 21 | pc := 0 |
| 22 | value := u8(0x0f) |
| 23 | |
| 24 | address := u16(rom[pc + 2]) << 8 | u16(rom[pc + 1]) |
| 25 | ram[address] = value |
| 26 | assert ram[0x0012] == value |
| 27 | assert ram[0] == 0 |
| 28 | |
| 29 | mut ram2 := [0x10000]u8{} |
| 30 | ram2[u16(rom[pc + 2]) << 8 | u16(rom[pc + 1])] = value |
| 31 | assert ram2[0x0012] == value |
| 32 | assert ram2[0] == 0 |
| 33 | } |
| 34 | |
| 35 | struct MemoryState { |
| 36 | mut: |
| 37 | a u8 |
| 38 | pc int |
| 39 | ram [0x10000]u8 |
| 40 | rom [4]u8 |
| 41 | } |
| 42 | |
| 43 | fn (mut state MemoryState) write_with_temp() { |
| 44 | address := u16(state.rom[state.pc + 2]) << 8 | u16(state.rom[state.pc + 1]) |
| 45 | state.ram[address] = state.a |
| 46 | } |
| 47 | |
| 48 | fn (mut state MemoryState) write_inline() { |
| 49 | state.ram[u16(state.rom[state.pc + 2]) << 8 | u16(state.rom[state.pc + 1])] = state.a |
| 50 | } |
| 51 | |
| 52 | fn test_inline_struct_fixed_array_index_assign_uses_full_expression() { |
| 53 | mut temp_state := MemoryState{ |
| 54 | a: 0x0f |
| 55 | pc: 0 |
| 56 | rom: [u8(0x00), 0x12, 0x00, 0x00]! |
| 57 | } |
| 58 | temp_state.write_with_temp() |
| 59 | assert temp_state.ram[0x0012] == temp_state.a |
| 60 | assert temp_state.ram[0] == 0 |
| 61 | |
| 62 | mut inline_state := MemoryState{ |
| 63 | a: 0x0f |
| 64 | pc: 0 |
| 65 | rom: [u8(0x00), 0x12, 0x00, 0x00]! |
| 66 | } |
| 67 | inline_state.write_inline() |
| 68 | assert inline_state.ram[0x0012] == inline_state.a |
| 69 | assert inline_state.ram[0] == 0 |
| 70 | } |
| 71 | |