| 1 | /* |
| 2 | * Copyright (c) 2003-2011 Hewlett-Packard Development Company, L.P. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 20 | * SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * This file specifies Itanimum primitives for use with the HP compiler |
| 25 | * under HP/UX. We use intrinsics instead of the inline assembly code in the |
| 26 | * gcc file. |
| 27 | */ |
| 28 | |
| 29 | #include "../all_atomic_load_store.h" |
| 30 | |
| 31 | #include "../all_acquire_release_volatile.h" |
| 32 | |
| 33 | #include "../test_and_set_t_is_char.h" |
| 34 | |
| 35 | #include <machine/sys/inline.h> |
| 36 | |
| 37 | #ifdef __LP64__ |
| 38 | # define AO_T_FASIZE _FASZ_D |
| 39 | # define AO_T_SIZE _SZ_D |
| 40 | #else |
| 41 | # define AO_T_FASIZE _FASZ_W |
| 42 | # define AO_T_SIZE _SZ_W |
| 43 | #endif |
| 44 | |
| 45 | AO_INLINE void |
| 46 | AO_nop_full(void) |
| 47 | { |
| 48 | _Asm_mf(); |
| 49 | } |
| 50 | #define AO_HAVE_nop_full |
| 51 | |
| 52 | #ifndef AO_PREFER_GENERALIZED |
| 53 | AO_INLINE AO_t |
| 54 | AO_fetch_and_add1_acquire (volatile AO_t *p) |
| 55 | { |
| 56 | return _Asm_fetchadd(AO_T_FASIZE, _SEM_ACQ, p, 1, |
| 57 | _LDHINT_NONE, _DOWN_MEM_FENCE); |
| 58 | } |
| 59 | #define AO_HAVE_fetch_and_add1_acquire |
| 60 | |
| 61 | AO_INLINE AO_t |
| 62 | AO_fetch_and_add1_release (volatile AO_t *p) |
| 63 | { |
| 64 | return _Asm_fetchadd(AO_T_FASIZE, _SEM_REL, p, 1, |
| 65 | _LDHINT_NONE, _UP_MEM_FENCE); |
| 66 | } |
| 67 | #define AO_HAVE_fetch_and_add1_release |
| 68 | |
| 69 | AO_INLINE AO_t |
| 70 | AO_fetch_and_sub1_acquire (volatile AO_t *p) |
| 71 | { |
| 72 | return _Asm_fetchadd(AO_T_FASIZE, _SEM_ACQ, p, -1, |
| 73 | _LDHINT_NONE, _DOWN_MEM_FENCE); |
| 74 | } |
| 75 | #define AO_HAVE_fetch_and_sub1_acquire |
| 76 | |
| 77 | AO_INLINE AO_t |
| 78 | AO_fetch_and_sub1_release (volatile AO_t *p) |
| 79 | { |
| 80 | return _Asm_fetchadd(AO_T_FASIZE, _SEM_REL, p, -1, |
| 81 | _LDHINT_NONE, _UP_MEM_FENCE); |
| 82 | } |
| 83 | #define AO_HAVE_fetch_and_sub1_release |
| 84 | #endif /* !AO_PREFER_GENERALIZED */ |
| 85 | |
| 86 | AO_INLINE AO_t |
| 87 | AO_fetch_compare_and_swap_acquire(volatile AO_t *addr, AO_t old_val, |
| 88 | AO_t new_val) |
| 89 | { |
| 90 | _Asm_mov_to_ar(_AREG_CCV, old_val, _DOWN_MEM_FENCE); |
| 91 | return _Asm_cmpxchg(AO_T_SIZE, _SEM_ACQ, addr, |
| 92 | new_val, _LDHINT_NONE, _DOWN_MEM_FENCE); |
| 93 | } |
| 94 | #define AO_HAVE_fetch_compare_and_swap_acquire |
| 95 | |
| 96 | AO_INLINE AO_t |
| 97 | AO_fetch_compare_and_swap_release(volatile AO_t *addr, AO_t old_val, |
| 98 | AO_t new_val) |
| 99 | { |
| 100 | _Asm_mov_to_ar(_AREG_CCV, old_val, _UP_MEM_FENCE); |
| 101 | return _Asm_cmpxchg(AO_T_SIZE, _SEM_REL, addr, |
| 102 | new_val, _LDHINT_NONE, _UP_MEM_FENCE); |
| 103 | } |
| 104 | #define AO_HAVE_fetch_compare_and_swap_release |
| 105 | |
| 106 | AO_INLINE unsigned char |
| 107 | AO_char_fetch_compare_and_swap_acquire(volatile unsigned char *addr, |
| 108 | unsigned char old_val, unsigned char new_val) |
| 109 | { |
| 110 | _Asm_mov_to_ar(_AREG_CCV, old_val, _DOWN_MEM_FENCE); |
| 111 | return _Asm_cmpxchg(_SZ_B, _SEM_ACQ, addr, |
| 112 | new_val, _LDHINT_NONE, _DOWN_MEM_FENCE); |
| 113 | } |
| 114 | #define AO_HAVE_char_fetch_compare_and_swap_acquire |
| 115 | |
| 116 | AO_INLINE unsigned char |
| 117 | AO_char_fetch_compare_and_swap_release(volatile unsigned char *addr, |
| 118 | unsigned char old_val, unsigned char new_val) |
| 119 | { |
| 120 | _Asm_mov_to_ar(_AREG_CCV, old_val, _UP_MEM_FENCE); |
| 121 | return _Asm_cmpxchg(_SZ_B, _SEM_REL, addr, |
| 122 | new_val, _LDHINT_NONE, _UP_MEM_FENCE); |
| 123 | } |
| 124 | #define AO_HAVE_char_fetch_compare_and_swap_release |
| 125 | |
| 126 | AO_INLINE unsigned short |
| 127 | AO_short_fetch_compare_and_swap_acquire(volatile unsigned short *addr, |
| 128 | unsigned short old_val, |
| 129 | unsigned short new_val) |
| 130 | { |
| 131 | _Asm_mov_to_ar(_AREG_CCV, old_val, _DOWN_MEM_FENCE); |
| 132 | return _Asm_cmpxchg(_SZ_B, _SEM_ACQ, addr, |
| 133 | new_val, _LDHINT_NONE, _DOWN_MEM_FENCE); |
| 134 | } |
| 135 | #define AO_HAVE_short_fetch_compare_and_swap_acquire |
| 136 | |
| 137 | AO_INLINE unsigned short |
| 138 | AO_short_fetch_compare_and_swap_release(volatile unsigned short *addr, |
| 139 | unsigned short old_val, |
| 140 | unsigned short new_val) |
| 141 | { |
| 142 | _Asm_mov_to_ar(_AREG_CCV, old_val, _UP_MEM_FENCE); |
| 143 | return _Asm_cmpxchg(_SZ_B, _SEM_REL, addr, |
| 144 | new_val, _LDHINT_NONE, _UP_MEM_FENCE); |
| 145 | } |
| 146 | #define AO_HAVE_short_fetch_compare_and_swap_release |
| 147 | |
| 148 | #ifndef __LP64__ |
| 149 | # define AO_T_IS_INT |
| 150 | #endif |
| 151 | |
| 152 | #undef AO_T_FASIZE |
| 153 | #undef AO_T_SIZE |
| 154 | |